The invention generally relates to a programmable logic array (PLA). More particularly, the invention relates to a PLA of improved functional and physical integration density.
Programmable logic arrays are known in various forms, e.g. from the book "MOS/LSI Design and Application" by W. Carr and J. Mice, McGrau-Hill, l972, pp. 229 to 258. By means of a progrmmable logic array, combinatorial logic can be directly implemented in regular structures, particularly in matrix arrangements. Compared with earlier logic circuits which were not provided in regular structures, PLA's facilitate mass production as well as testing and stock keeping.
Beside programmable logic arrays whose logic or data pattern is permanently impressed during production, with no subsequent modifications being possible, there also have been described programmable logic arrays permitting alteration after manufacture. U.S. Pat. No. 3,987,286 assigned to the assignee of the present invention is an example of such an arrangement. There, through time-controlled release or inhibition of logic circuits of the matrix arrangements, different logic functions can be executed in one and the same PLA. This arrangement requires, however, that personalization data must be stored in additionally required shift register elements.
Further, multi-personalizations with specific coupling and logic elements are known which can adopt several states. Reference is made in this connection to IBM Technical Disclosure Bulletin, Vol. 17, No. 3, August 1974, pp. 811 and 812. However, owing to the components, and the low operational speed these concepts were not fully satisfactory.
From IBM Technical Disclosure Bulletin, Vol. 20, No. 10, March 1978, pp. 4016 to 4018, and U.S. Pat. No. 4,084, 152, highly integrated programmable logic circuit arrays are known, where remaining unused logic areas, i.e. redundant circuits, are reduced. A disadvantage of these circuit arrangements, however, is that they impose considerable restrictions on the expert when designing complex logic networks. This means that the high amount of flexibility from regular structures is lost with the consequences that the possible application field of this type of programmable logic arrays is very limited.
In applicant's co-pending U.S. patent application, Ser. No. 317,699 filed Nov. 2, 1981 and assigned to the assignee of the present invention which is now U.S. Pat. No. 4,445,202, a further improvement of these programmable logic arrays is disclosed which permits a higher functional density as well as a rapid electrical switching between different functions while avoiding the need for high re-programming voltages or specific circuit elements. More particularly, array logic or coupling elements are one-device FET cells whose gate electrodes are patterned in accordance with a respective personalization state at that particular crosspoint. For instance, in a two-fold personalization PLA, the coupling elements consist of FET's with two gate sections provided one beside the other. For a connection to be established in only one of the two possible functions at the respective crosspoint, one of the gate sections is connected to a control line provided for the functional selection. The remaining gate section is connected to the associated input line. A connection in the other functional mode is provided correspondingly with only the control lines being switched. If at the respective crosspoint a connection is to be effective in both functional modes, both gate sectiions are jointly connected to the respective input line. Although this type of a PLA offers a high semiconductor surface utilization and is therefore suitable for highly integrated structures, it is still desirable to take advantage of the relatively high amount of remaining redundant components or Don't Care positions in such a PLA structure.
Accordingly, it is an object of the invention to provide a programmable logic array with a further increased functional density.
It is another object of this invention to provide a programmable logic array with a quick electrical switching capability between different stored functions without a need for high voltages or special cell components for re-programming.
Yet another object of the invention is to provide in a highly integrated programmable logic array the activation of available redundant or Don't Care states of array cells.